Today, prescalers are commonly used in phased locked loop (PLL) structures. Typically, prescalers with a variety of frequency divisions and an approximate 50% duty cycle are employed. Most designs for these prescalers are relatively straightforward. Some examples of these designs are U.S. Pat. Nos. 3,530,284; 4,703,495; 5,867,068; and 7,119,587 and U.S. Patent Pre-Grant Pub. Nos. 2002/0114422 and 2008/0186062.
However, divide-by-three prescalers are of interest. Turning to FIG. 1, the desired clock signal for a divide-by-three prescaler can be seen. The input clock signal CLKIN would correspond to an output signal from a voltage controlled oscillator (VCO) into a prescaler, and the output clock signal CLKOUT would correspond to input clock signal CLKIN divided by three. As can be seen in FIG. 1, the output clock signal CLKOUT has a 50% duty cycle with symmetrical rise and fall times.
Over the years, there have been numerous designs for divide-by-three prescalers with a 50% duty cycle. Some examples are U.S. Pat. Nos. 3,439,278; 3,943,379; 3,902,125; 4,348,640; 4,366,394; and 6,389,095. Many of these designs, though, are not particularly applicable to CML, which uses synthesized frequencies above 1 GHz.
Therefore, there is a need for a divide-by-three prescaler that is compatible and applicable to CML.